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Brief analysis of typical ESD damage risk in IC packaging and testing factory

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2019-12-09
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                   Brief analysis of typical ESD damage risk in IC packaging and testing factory

ESD(Electro-Static DischargeVVIP)IC(Integrated Circuit)CDM(Charged Device Model)The electronics manufacturing industry's need for ESD protection is completely generated with the birth of IC microelectronic devices and the development of IC technology and processes. The reason why ICs are sensitive to ESD is that a large number of MOS tube structures in the main IC structure are the most sensitive to ESD. To be precise, each insulation layer (most commonly SiO2) in MOS tubes is most easily damaged by static electricity.


Taking SiO2 as an example, the maximum electrostatic effect it can withstand is an electrostatic field of -5E8 V / m. Taking 100nm thick SiO2 as an example, when the corresponding static voltage reaches 50 V, the SiO2 insulation layer is easily damaged by electrostatic breakdown (from perfect insulation to semiconductor or conductor characteristics). Many current IC devices in the industry have adopted a few nm process technology, and the static voltage that the internal insulation layer can withstand is reduced to a few V. (Current IC products can withstand hundreds of V of static electricity. Corresponding ESD protection is added internally Circuit)


The most typical ESD damage situation in the IC packaging and testing process is the CDM ESD, which is concentrated in the Wire bonding process and various power-on inspection processes (such as Functional testing, Burn-in). Its ESD mechanism is briefly described as:
1) The CDM ESD situation of the wire bonding process: Due to the high static electricity on the operation band of the previous process, electrostatic discharge occurs when it is connected to the ground wire of the wire bonder.
2) The CDM ESD situation of the electrical test process: The IC has high static electricity due to the operation of the previous process or the operation of the IC loading to the test sockets, and the pins / pads of the IC are in contact with the ground test pins of the electrical test machine. When it is turned on (often when a pin is turned on first), an electrostatic discharge occurs.


For IC packaging and testing factories to deal with CD / ESD damage to Die / IC, the main solution is to adopt feasible measures to reduce the electrostatic charge level of Die / IC, especially at the critical moment when electrostatic discharge occurs.


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