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IrDA test socket

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2018-04-11
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IrDA infrared function

The IrDA mode is selected by setting the IREN bit of the UART_CR5 register. The STOP bit of the UART_CR3 register must be set to "1 stop bit". In IRDA mode, the following bits must be kept clear:

LINE_, STOP, and CLKEN bits of the UART_CR3 register
The SCEN and HDSEL bits of the UART_CR5 register.
Note: The STM8 IR function is only available for UART1 and UART2.

The IrDA SIR physical layer specifies the use of an inverse zero modulation scheme (RZI), which uses an infrared light pulse to represent a logical '0' (see Figure 114).

The SIR transmit encoder modulates the NRZ (non-return-to-zero) bitstream output from the UART. The output pulse stream is transmitted to an external output driver and infrared LED. For SIR ENDEC applications, the UART only supports up to 115.2Kbps. In normal mode, the pulse width is specified as 3/16 of a bit period.

The SIR receiver decoder demodulates the return bit stream from the infrared receiver and outputs the received NRZ serial bit stream to the UART. In the idle state, the decoder input is usually high (marking state marking state). The polarity of the transmit encoder output is the opposite of the decoder input. When the decoder input is low, a start bit is detected.

IrDA is a half-duplex communication protocol. If the transmitter is busy (that is, the UART is sending data to the IrDA encoder), any data on the IrDA receiver line will be ignored by the IrDA decoder. If the receiver is busy (that is, the UART is receiving decoded data from the IrDA decoder), the data from the UART's TX to IrDA will not be encoded by IrDA. When receiving data, sending should be avoided because the data to be sent may be corrupted.
The SIR transmit logic sends '0' as a high pulse and '1' as a low level. The width of the pulse is defined as 3/16 of the bit period in normal mode (see Figure 115).
The SIR decoder converts the received IrDA signal into a bit stream and sends it to the UART.
The SIR reception logic interprets the high state as '1' and the low pulse as '0'.
The send encoder output has the opposite polarity to the decoder input. When idle, the SIR output is low.
The IrDA specification requires that the pulse be wider than 1.41us. Pulse width is programmable. The receiver-side spike detection circuit filters the pulses that are less than 2 PSC cycles in width (PSC is the prescaler value programmed in UART_GTPR). Pulses less than 1 PSC cycle in duration must be filtered out, but pulses larger than 1 and less than 2 PSC cycles in duration may be received or filtered. Those with width greater than 2 cycles will be considered as a valid pulse. . When PSC=0, the IrDA encoder/decoder does not work.
The receiver can communicate with a low-power transmitter.
In IrDA mode, the STOP bit on the UART_CR2 register must be configured as a stop bit.
IrDA infrared low power mode

IrDA can work in normal mode or low power mode. Selecting the low power mode requires setting the IRLP bit of the UART_CR5 register.

Transmitter

In low power mode, the pulse width no longer lasts 3/16 bit cycles. Instead, the pulse width is 3 times lower than the low-power baud rate clock cycle, which can be a minimum of 1.42 MHz. This value is usually 1.8432 MHz (1.42 MHz
receiver

Reception in the low power mode is similar to normal mode reception.
In order to filter out the spike interference pulses, the UART should filter out pulses shorter than one cycle in length. Only the low-level signal of the IrDA low power baud rate clock (PSC in UART_GTPR) that lasts longer than 2 cycles is accepted as a valid signal.
Note: 1. Pulses less than 2 pulses greater than 1 PSC cycle may or may not be filtered out.
2. The receiver setup time should be managed by the software. The IrDA physical layer specification specifies a minimum 10 ms delay between transmission and reception (IrDA is a half-duplex).

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